The data transfer speed between memory chips and controller chips has significantly increased with the introduction of double data rate (DDR) memory chips. To achieve this speed increase, DDR memory chips employ a data strobe (DQS) signal which allows data to be latched from a data bus by a receiver (e.g., a memory chip, or a controller chip that controls the memory chip) on both the rising and the falling edge of the DQS. Specifically, during data transfer, data and the DQS are driven from a source (e.g., a controller chip during a "write" operation or a memory chip during a "read" operation) to a receiver (e.g., a memory chip during a write operation or a controller chip during a we read operation). The receiver latches one bit of data into a first rising edge register in response to each DQS rising edge, and latches one bit of data into a first falling edge register in response to each DQS falling edge. As used herein, "in response to" means in direct response to a signal, in response to the inverse of the signal or in response to a combination of the signal with one or more other signals.
Once a data bit has been latched by the receiver, the data bit is synchronized to the receiver's internal clock. To achieve data bit synchronization, between each successive DQS rising edge, the data bit stored within the first rising edge register is latched into a second rising edge register in response to the receiver's internal clock. Similarly, between each DQS falling edge, the data bit stored within the first falling edge register is latched into a second falling edge register in response to the receiver's internal clock. Data synchronization of both rising and falling edge data thereby is achieved.
Following data transfer, a source and its associated receiver may wish to reverse roles (e.g., a controller chip may wish to switch from a read operation to a write operation or vice versa), or a controller chip presently controlling a data bus may wish to relinquish the data bus to another controller. To switch between read and write operations, or to relinquish control of a data bus, following the last falling edge of the DQS, the source holds the DQS at a low voltage level for one half of a clock cycle (i.e., the postamble) and then "releases" the DQS to a floating state. Thereafter, another chip may drive the DQS.
Once released, the DQS may float to any voltage level. In many instances the released DQS oscillates and generates unintended DQS rising and falling edge transitions. Because the last "intentional" DQS transition is always a falling edge transition (which occurs immediately preceding the postamble and which latches the last transferred data bit into the first falling edge register), an unintended DQS falling edge immediately following the postamble can latch corrupt data into the first falling edge register before the last transferred data bit stored therein is latched into the second falling edge register. Corrupt data, instead, is latched into the second falling edge register in response to the receiver's internal clock. This form of data corruption ("postamble corruption") can occur following each postamble and is a serious drawback to the significant speed gains associated with DDR memory chips.
One solution to postamble corruption is to extend the postamble time period to a full clock cycle. A full clock cycle postamble guarantees that the last data bit stored within the first falling edge register is transferred to the second falling edge register before the DQS is released. This solution, however, has been rejected by DDR manufacturers because a longer postamble increases the time required to switch between read and write operations and thus decreases overall memory system throughput.
Accordingly, a need exists for a method and apparatus for preventing postamble corruption within a memory system. Such a method and apparatus will greatly advance the benefits of DDR memory chips by providing postamble corruption free data transfer.